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Device Overview MC9S12G-Family
Table 1-2. Maximum Peripheral Availability per Package
Peripheral
8-Bit PWM Channels
ADC channels
DAC0
DAC1
ACMP
Total GPIO
20 TSSOP
4=0…3
6=0…5
—
—
Yes
14
32 LQFP
6=0…5
8=0…7
—
—
Yes
26
48 LQFP,
48 QFN
8=0…7
12 = 0 … 11
Yes
Yes
Yes
40
64 LQFP
8=0…7
16 = 0 … 15
Yes
Yes
Yes
54
100 LQFP
8=0…7
16 = 0 … 15
Yes
Yes
—
86
KGD (Die)
8=0…7
16 = 0 … 15
Yes
Yes
—
86
1.2.2
Chip-Level Features
On-chip modules available within the family include the following features:
? S12 CPU core
? Up to 240 Kbyte on-chip ?ash with ECC
? Up to 4 Kbyte EEPROM with ECC
? Up to 11 Kbyte on-chip SRAM
? Phase locked loop (IPLL) frequency multiplier with internal ?lter
? 4–16 MHz amplitude controlled Pierce oscillator
? 1 MHz internal RC oscillator
? Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture,
output compare, counter, and pulse accumulator functions
? Pulse width modulation (PWM) module with up to eight x 8-bit channels
? Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter
(ADC)
? Up to two 8-bit digital-to-analog converters (DAC)
? Up to one 5V analog comparator (ACMP)
? Up to three serial peripheral interface (SPI) modules
? Up to three serial communication interface (SCI) modules supporting LIN communications
? Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol
2.0A/B)
? On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
? Autonomous periodic interrupt (API)
? Precision ?xed voltage reference for ADC conversions
? Optional reference voltage attenuator module to increase ADC accuracy
1.3
Module Features
The following sections provide more details of the modules implemented on the MC9S12G-Family family.
MC9S12G Family Reference Manual, Rev.1.23
42
Freescale Semiconductor
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